Thin-film transistor substrate and liquid crystal display

ABSTRACT

A channel layer is formed of an oxide semiconductor. A first insulating film is provided on the channel layer, a source line, and a drain electrode, and includes a drain contact hole which reaches the drain electrode. A pixel electrode is provided on the first insulating film, includes a connection conductive layer which is connected to the drain electrode by the drain contact hole, and is formed of a transparent conductive material. The pixel electrode is covered with a second insulating film. A common electrode is provided on the second insulating film, includes an opening which faces the pixel electrode in a thickness direction, and is formed of a transparent conductive material. A metal layer, in conjunction with a part of the common electrode, forms a laminated structure, and includes a light-shield part which overlaps the channel layer at least partially in plan view.

BACKGROUND OF THE INVENTION Field of the Invention

The present invention relates to a thin-film transistor substrate and aliquid crystal display, and particularly to a thin-film transistorsubstrate and a liquid crystal display which use an oxide semiconductor.

Description of the Background Art

A TFT active matrix substrate (or a thin-film transistor substrate,which will hereinafter be referred to as a “TFT substrate”) which uses aplurality of thin-film transistors (TFT) arranged in a matrix, asswitching devices, is utilized in an electrooptical apparatus such as adisplay using liquid crystal (liquid crystal display which willhereinafter be also referred to as an “LCD”), or a display using a lightemitting diode (LED) (light-emitting display), for example. As an LCD, aTFT-LCD using a TFT as a switching device and a simple matrix LCD areavailable, and a TFT-LCD is superior to a simple matrix LCD in displayquality. For this reason, a TFT-LCD is widely used in display productsincluding a mobile computer, a notebook-sized personal computer, atelevision, and the like. A TFT-LCD includes a TFT substrate, a countersubstrate in which a color filter or the like is provided, and a liquidcrystal layer held between those substrates. A polarizing plate isprovided on each of a front surface and a back surface of the TFT-LCD,and a backlight is provided on an outside of either a front surface or aback surface of the TFT-LCD.

As a mode of driving liquid crystal in an LCD, a vertical electric fieldmode such as a twisted nematic (TN) mode or a vertical alignment (VA)mode, and a transverse electric field mode such as an in-plane switching(IPS) mode (“IPS” is a registered trademark) or a fringe field shielding(FFS) mode, are available. In a liquid crystal display for a verticalelectric field mode typified by a TN mode, a pixel electrode to which avoltage corresponding to a pixel signal is applied is provided in a TFTsubstrate, and a common electrode kept at a constant potential (commonpotential) is provided in a counter substrate. Accordingly, liquidcrystal in a liquid crystal layer is driven by an electric field whichis substantially perpendicular to a surface of a liquid crystal display.On the other hand, in a liquid crystal display for a transverse electricfield mode, both of a pixel electrode and a common electrode areprovided in a TFT substrate. Liquid crystal in a liquid crystal layer isdriven by an electric field which is substantially horizontal to asurface of a liquid crystal display. More specifically, in a TFTsubstrate for an FFS mode, a pixel electrode and a common electrode areplaced so as to vertically face each other via an insulating layer.Either a pixel electrode or a common electrode can be placed on a lowerside (farther from a liquid crystal layer). One of a pixel electrode anda common electrode which is placed on a lower side (a side farther froma liquid crystal layer) is formed into a plate-like shape, and the otherwhich is placed on an upper side (a side closer to a liquid crystallayer) is formed into a grid shape having a slit or a comb-like shape.In general, a liquid crystal display for a transverse electric fieldmode is advantageous over a liquid crystal display for a verticalelectric field mode in obtaining a wide viewing angle, and so isbecoming predominant in a field of a display product such as a personalcomputer or an on-vehicle display equipment.

As a semiconductor material of a TFT substrate, amorphous silicon (a-Si)has been widely used so far. In such a situation, various modes ofdriving liquid crystal have been used. For example, Japanese PatentApplication Laid-Open No. 10-268353 (1998) discloses a TFT substrate fora TN mode. Such a TFT substrate can be generally manufactured by fivephotoengraving processes of: (1) forming a gate electrode; (2) forming agate insulating film and a channel layer; (3) forming a source electrodeand a drain electrode; (4) forming a contact hole through a protectiveinsulating film; and (5) forming a pixel electrode. Also, JapanesePatent Application Laid-Open No. 2009-151285, for example, discloses aTFT substrate for an FFS mode. Such a TFT substrate can be generallymanufactured by seven photoengraving processes of: (1) forming a gateelectrode; (2) forming a gate insulating film and a channel layer; (3)forming a source electrode and a drain electrode; (4) forming a contacthole through a protective insulating film; (5) forming a pixelelectrode; (6) forming a contact hole through an interlayer insulatingfilm; and (7) forming a common electrode.

A pixel electrode and a common electrode which are separated from a TFTby an insulating film are provided in each of pixel units of a TFTsubstrate for an FFS mode. An arbitrary signal (voltage) which isexternally provided and indicates displayed information is applied to apixel electrode from a signal line via a TFT and a contact hole formedin an insulating film. In this regard, an area actually used fordisplaying in a pixel unit (hereinafter, an area used for displaying ina pixel unit will be referred to as a “display-pixel area”) is an areawhere a common electrode and a pixel electrode are superimposed. On theother hand, an area where a TFT, a contact hole, a signal line, and ascanning line are placed is an area which is not used for displaying(which will hereinafter be referred to as a “non-display-pixel area”).In a pixel unit, an increase of a proportion of a non-display-pixel areameans a decrease of a proportion of a display-pixel area. That is, anincrease of a proportion of a non-display-pixel area means reduction inaperture ratio. Reduction in aperture ratio hampers enhancement indefinition of a display. Therefore, it is desired to minimize anon-display-pixel area.

In recent years, “Room-temperature fabrication of transparent flexiblethin-film transistors using amorphous oxide semiconductors”, KenjiNomura et al, Nature 2004, Vol. 432, pp. 488-492 discloses usability ofan oxide semiconductor as a semiconductor material of a TFT. An oxidesemiconductor, which has higher mobility than conventionally-used a-Si,allows reduction in size of a TFT while maintaining a performance. Thus,an oxide semiconductor is advantageous in ensuring an aperture ratiostated above. For this reason, an oxide semiconductor is beginning to beapplied to a portable equipment such as a smartphone or a mobilecomputer, a personal computer, and the like. As an oxide semiconductor,a zinc-oxide- (ZnO—) based material, or an amorphous InGaZnO-basedmaterial which is ZnO doped with a gallium oxide (Ga₂O₃) and an indiumoxide (In₂O₃), is mainly used. The foregoing techniques are disclosed inJapanese Patent Application Laid-Open No. 2005-77822 and Japanese PatentApplication Laid-Open No. 2007-281409, and the like, for example.

Generally, an oxide semiconductor is easily deteriorated due to lightsuch as UV light. As such, it is conceived to prevent an influence oflight incidence from above by provision of a film serving to block lightabove an oxide semiconductor. For example, according to Japanese PatentApplication Laid-Open No. 2013-122536, a common electrode is provided ona TFT using an oxide semiconductor via an insulating film in a TFTsubstrate for an FFS mode. A light-shield conductor is provided on apart of the common electrode. Then, a pixel electrode formed of atransparent conductive material is provided on the light-shieldconductor via another insulating film. The pixel electrode is connectedto a drain electrode of the TFT via a contact hole passing through bothof the insulating films. The light-shield conductor serves to not onlyblock light as described above, but also reduce electrical resistance ofan electrical path across the common electrode. Reduction in electricalresistance can lead to acquisition of more excellent image quality.

According to the above-described techniques in Japanese PatentApplication Laid-Open No. 2013-122536, the common electrode is placedbetween the TFT and the pixel electrode formed of a transparentconductive material, in a thickness direction. Thus, an electrical pathbetween the TFT and the pixel electrode is lengthened. Also, theforegoing electrical path is formed of a transparent conductivematerial, which has higher resistivity than resistivity of a metalmaterial. Thus, electrical resistance of the electrical path is likelyto increase. Due to that, defective displaying is likely to occur. Toincrease an area of a contact hole forming the electrical path allowsreduction in electrical resistance on one hand. However, to do soresults in an increase in an area of a non-display-pixel area.Consequently, an aperture ratio is reduced. As described above, in theconventional art, it is difficult to suppress occurrence of defectivedisplaying while ensuring a sufficient aperture ratio.

SUMMARY OF THE INVENTION

The present invention has been made to solve the above-describedproblems, and it is an object of the present invention to provide athin-film transistor substrate and a liquid crystal display which cansuppress occurrence of defective displaying while ensuring an apertureratio.

A thin-film transistor substrate according to one aspect of the presentinvention includes a display area having a plurality of pixels which arearranged in a matrix. The thin-film transistor substrate includes asupporting substrate, a gate line, a gate insulating film, a channellayer, a source line, a drain electrode, a first insulating film, apixel electrode, a second insulating film, a common electrode, and ametal layer. The gate line is provided on the supporting substrate andincludes a gate electrode placed in each of the pixels. The gate line iscovered with the gate insulating film. The channel layer is provided oneach of the gate electrodes via the gate insulating film and is formedof an oxide semiconductor. The source line is placed in each of thepixels and includes a source electrode which is in contact with thechannel layer. The drain electrode is placed in each of the pixels, isin contact with the channel layer, and is distant from the sourceelectrode. The first insulating film is provided on the channel layer,the source line, and the drain electrode, and includes a drain contacthole which reaches the drain electrode. The pixel electrode is providedon the first insulating film in each of the pixels, includes aconnection conductive layer electrically connected to the drainelectrode by the drain contact hole, and is formed of a transparentconductive material. The pixel electrode is covered with the secondinsulating film. The common electrode is provided on the secondinsulating film, includes an opening facing the pixel electrode in athickness direction, and is formed of a transparent conductive material.The metal layer forms a laminated structure in conjunction with a partof the common electrode, and includes a light-shield part which overlapsthe channel layer at least partially in plan view.

A thin-film transistor substrate according to another aspect of thepresent invention includes a display area having a plurality of pixelswhich are arranged in a matrix. The thin-film transistor substrateincludes a supporting substrate, a gate line, a gate insulating film, achannel layer, a source line, a drain electrode, a first insulatingfilm, a pixel electrode, a metal layer, a second insulating film, and acommon electrode. The gate line is provided on the supporting substrateand includes a gate electrode placed in each of the pixels. The gateline is covered with the gate insulating film. The gate insulating filmincludes a first gate contact hole which reaches the gate line. Thechannel layer is provided on each of the gate electrodes via the gateinsulating film and is formed of an oxide semiconductor. The source lineis placed in each of the pixels and includes a source electrode which isin contact with the channel layer. The drain electrode is placed in eachof the pixels, is in contact with the channel layer, and is distant fromthe source electrode. The first insulating film is provided on thechannel layer, the source line, and the drain electrode, and includes asecond gate contact hole which is joined to the first gate contact hole,and includes a drain contact hole which reaches the drain electrode. Thepixel electrode is provided on the first insulating film in each of thepixels, includes a connection conductive layer electrically connected tothe drain electrode by the drain contact hole, and is formed of atransparent conductive material. The metal layer is provided on a partof the first insulating film and includes a light-shield part whichoverlaps the channel layer at least partially in plan view. The pixelelectrode and the metal layer are covered with the second insulatingfilm. The common electrode is provided on the second insulating film,includes an opening facing the pixel electrode in a thickness direction,and is formed of a transparent conductive material. The metal layer iselectrically connected to the gate line by the first gate contact holeand the second gate contact hole.

In the thin-film transistor substrate according to one aspect of thepresent invention, the common electrode need not be placed between theTFT and the pixel electrode formed of a transparent conductive materialin a thickness direction. This can allow an electrical path between theTFT and the pixel electrode to be made shorter than that in a case wherethe common electrode is placed between the TFT and the pixel electrode.This can reduce an area of a contact hole forming the above-statedelectrical path, while preventing electrical resistance of theelectrical path from excessively increasing. Accordingly, an area of anon-display-pixel area can be reduced. Thus, a high aperture ratio canbe easily ensured. Further, firstly, the metal layer including thelight-shield part which blocks light travelling toward the channel layeris provided. This suppresses deterioration of the channel layer formedof an oxide semiconductor, which is caused due to light. Thus, defectivecontrol of displaying which is caused due to deterioration of thechannel layer is suppressed. Secondly, the metal layer, in conjunctionwith a part of the common electrode, forms a laminated structure. Thislaminated structure forms an electrical path having low resistance. As aresult of this, a potential difference in the common electrode withinthe TFT substrate is reduced. Thus, unevenness in displaying of adisplay using the TFT substrate is suppressed. Based on theabove-described matters, it is possible to suppress occurrence ofdefective displaying while ensuring an aperture ratio.

In the thin-film transistor substrate according to another aspect of thepresent invention, the common electrode need not be placed between theTFT and the pixel electrode formed of a transparent conductive materialin a thickness direction. This can allow an electrical path between theTFT and the pixel electrode to be made shorter than that in a case wherethe common electrode is placed between the TFT and the pixel electrode.This can reduce an area of a contact hole forming the foregoingelectrical path, while preventing electrical resistance of theelectrical path from excessively increasing. Accordingly, an area of anon-display-pixel area can be reduced. Thus, a high aperture ratio canbe easily ensured. Further, firstly, the metal layer including thelight-shield part which blocks light travelling toward the channel layeris provided. This suppresses deterioration of the channel layer formedof an oxide semiconductor, which is caused due to light. Thus, defectivecontrol of displaying which is caused due to deterioration of thechannel layer is suppressed. Secondly, the metal layer is electricallyconnected to the gate electrode. This can prevent a high electric fieldfrom being generated between the light-shield part included in the metallayer and the gate electrode. Accordingly, the channel layer placedbetween the light-shield part and the gate electrode can be preventedfrom being deteriorated due to a high electric field. Thus, defectivecontrol of displaying which is caused due to deterioration of thechannel layer is further suppressed. Based on the above-describedmatters, it is possible to suppress occurrence of defective displayingwhile ensuring a sufficient aperture ratio.

These and other objects, features, aspects and advantages of the presentinvention will become more apparent from the following detaileddescription of the present invention when taken in conjunction with theaccompanying drawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a partial cross-sectional view schematically showing aconfiguration of a liquid crystal display according to a first preferredembodiment of the present invention;

FIG. 2 is a plan view schematically showing a configuration of athin-film transistor substrate in FIG. 1;

FIG. 3 is a partial plan view schematically showing a configuration ofeach of a plurality of pixels included in the thin-film transistorsubstrate in FIG. 2;

FIG. 4 is a view in the same field of view as that in FIG. 3, and is apartial plan view schematically showing the configuration of each of theplurality of pixels while omitting showing of a part of members;

FIG. 5 is a schematical partial cross-sectional view taken along a lineV-V in FIGS. 3 and 4;

FIG. 6 is a partial plan view schematically showing a configuration ofeach of a plurality of pixels included in a thin-film transistorsubstrate according to a second preferred embodiment of the presentinvention while omitting showing of a part of members;

FIG. 7 is a schematical partial cross-sectional view taken along a lineVII-VII in FIG. 6;

FIG. 8 is a partial plan view schematically showing a configuration ofeach of a plurality of pixels included in a thin-film transistorsubstrate according to a third preferred embodiment of the presentinvention while omitting showing of a part of members;

FIG. 9 is a schematical partial cross-sectional view taken along a lineIX-IX in FIG. 8;

FIG. 10 is a partial cross-sectional view schematically showing aconfiguration of a frame area of a thin-film transistor substrateaccording to a fifth preferred embodiment of the present invention; and

FIG. 11 is a partial cross-sectional view showing a modification of FIG.10.

DESCRIPTION OF THE PREFERRED EMBODIMENTS

Below, preferred embodiments of the present invention will be describedwith reference to the drawings. It is noted that the drawings provideschematic representation, and do not reflect exact sizes and the like ofcomponents shown therein. Also, for the sake of brevity in the drawings,the part other than a principal part of the present invention is omittedand a part of a configuration is shown in a simplified manner, asneeded. Further, in FIG. 2 and later, components which are identical orsimilar to components shown in the preceding drawings, are denoted bythe same reference symbols, and description thereof will be omitted.

First Preferred Embodiment

(Configuration of Liquid Crystal Display)

FIG. 1 is a partial cross-sectional view schematically showing aconfiguration of a liquid crystal display 500 according to a firstpreferred embodiment. The liquid crystal display 500 includes a TFTsubstrate 200 (thin-film transistor substrate), a color filter substrate300 (counter substrate), a liquid crystal layer 400, an alignment layer161, and an alignment layer 162. The color filter substrate 300 isplaced at a distance from the TFT substrate 200. The liquid crystallayer 400 is held between the TFT substrate 200 and the color filtersubstrate 300. Each of the alignment layer 161 and the alignment layer162 serves to cause alignment of the liquid crystal layer 400. Thealignment layer 161 and the alignment layer 162 are provided on the TFTsubstrate 200 and the color filter substrate 300, respectively. In thefirst preferred embodiment, the liquid crystal display 500 is of a typefor an FFS mode.

(Configuration of TFT Substrate)

FIG. 2 is a plan view schematically showing a configuration of the TFTsubstrate 200. The TFT substrate 200 includes a display area 101 wherean image is displayed, and a frame area 102 provided outside the displayarea 101. The frame area 102 surrounds the display area 101, typically,as shown in FIG. 2. Each of the alignment layers 161 and 162 (FIG. 1) isplaced so as to include at least the display area 101 in plan view.

The TFT substrate 200 includes a plurality of external lines 107, aplurality of terminal electrodes 108, and a plurality of integratedcircuit (IC) chips 109, all of which are placed in the frame area 102.It is noted that FIG. 2 shows only a single terminal electrode 108 forthe sake of convenience of drawing. The external line 107 extends fromeach of a signal line 103 (source line) and a scanning line 104 (gateline) in the display area 101 to the frame area 102. The terminalelectrode 108 is electrically connected to an end of the external line107 and has a larger width than a width of the end of the external line107. The terminal electrode 108 is a terminal used for externalconnection, and is placed so as to overlap external members such as theIC chip 109, a printed board 110, and the like in this preferredembodiment. As a result of this, the external members are electricallyconnected to the external line 107. A terminal of the IC chip 109 iselectrically connected to the terminal electrode 108 via a bump or ananisotropic conductive film (ACF). Similarly, a terminal of the printedboard 110 is electrically connected to the terminal electrode 108 via abump or an ACF.

In the display area 101, a plurality of signal lines 103, a plurality ofscanning lines 104, a plurality of TFTs 105 which are electricallyconnected to those lines, and a common line 106 are provided. Theplurality of signal lines 103 and the plurality of scanning lines 104are placed orthogonally to each other. One pixel PX1 is formed in eacharea which is surrounded by adjacent ones of the signal lines 103 andadjacent ones of the scanning lines 104. As a result of this, aplurality of pixels PX1 are arranged in a matrix. The TFT 105 isprovided in each of the plurality of pixels PX1. Accordingly, theplurality of TFTs 105 are arranged in a matrix.

(Configuration and Function of Pixel)

FIG. 3 is a partial plan view schematically showing a configuration ofeach of the pixels PX1. FIG. 4 is a view in the same field of view asthat in FIG. 3 and is a partial plan view schematically showing aconfiguration of each of the pixels PX1, while omitting showing of apart of members. FIG. 5 is a schematical partial cross-sectional viewtaken along a line V-V (FIGS. 3 and 4). It is noted that a metal layer15 is shown with a dot pattern in FIG. 4 for increased visibility.

The TFT substrate 200 includes a transparent insulating substrate 100(supporting substrate), the scanning lines 104, a gate insulating film2, a channel layer 31, the signal lines 103, a drain electrode 42, aninsulating film 20 (first insulating film), a pixel electrode 71, aninterlayer insulating film 8 (second insulating film), a commonelectrode 91, and the metal layer 15.

The scanning lines 104 are provided on the transparent insulatingsubstrate 100. In each of the pixels PX1, a partial area of the scanninglines 104 functions as a gate electrode 11. In other words, the scanninglines 104 include the gate electrodes 11 placed in the pixels PX1,respectively.

The scanning lines 104 are covered with the gate insulating film 2. Asthe gate insulating film 2, an SiN film, an SiO film, a laminated filmof SiO and SiN, or the like is used, for example.

The channel layer 31 is provided like an island on each of the gateelectrodes 11, via the gate insulating film 2. The channel layer 31 isformed of an oxide semiconductor. In general, an oxide semiconductor islikely to be deteriorated due to light.

The gate electrode 11, which is typically formed of a metal materialsuch as Al, Cu, Ni, Ag, Nd, Mo, or Nb, has a light-shield property.Because of this light-shield property, light of a backlight is preventedfrom being incident upon the channel layer 31 from a lower side in FIG.1, during operation of the liquid crystal display 500 (FIG. 1). In orderto enhance the foregoing effect, it is preferable that the channel layer31 be included in the gate electrode 11 in plan view.

The signal lines 103 (FIG. 4) are provided on the gate insulating film 2(FIG. 5). In each of the pixels PX1, a partial area of the signal lines103 functions as a source electrode 41. In other words, the signal lines103 include the source electrodes 41 placed in the pixels PX1,respectively. Each of the source electrodes 41 is in contact with thechannel layer 31 on one end of the channel layer 31.

The drain electrode 42 is placed in each of the pixels PX1. The drainelectrode 42 is in contact with the channel layer 31 on the other end ofthe channel layer 31, and is distant from the source electrode 41. Aportion of the channel layer 31, which is interposed between the sourceelectrode 41 and the drain electrode 42, functions as a channel regionof the TFT 105.

The insulating film 20 is provided so as to lie over the display area101 (FIG. 2) and the frame area 102 (FIG. 2). In the display area 101,the insulating film 20 is provided on the channel layers 31, the signallines 103, and the drain electrodes 42. In the insulating film 20, adrain contact hole 121 which reaches each of the drain electrodes 42 isprovided.

The insulating film 20 includes a protective insulating film 5 and aflattening film 6 which is stacked on the protective insulating film 5.A contact hole 51 and a contact hole 61 are provided in the protectiveinsulating film 5 and the flattening film 6, respectively. As a resultof those contact holes being joined, the above-stated drain contact hole121 is formed. In the frame area 102, the insulating film 20 is providedon the external lines 107. The gate insulating film 2 may extend betweenthe insulating film 20 and the external lines 107.

As the protective insulating film 5, an inorganic insulating film suchas an SiN film, a silicon oxide film (SiO film), or a laminated film ofSiN and SiO is used, for example. To use an inorganic insulating filmsuch as an SiN film, as the protective insulating film 5, could preventcharacteristics of the TFT 105 from being degraded due to moisture orthe like provided from the flattening film 6 or the like. In addition tothe foregoing effect, because of high mechanical strength of aninorganic insulating film, an effect of making it difficult to beexternally damaged can be achieved.

The flattening film 6 is placed on the TFT 105 via the protectiveinsulating film 5. The flattening film 6 has an upper surface which ismade flat. As the flattening film 6, an organic resin film may be used,for example. An organic resin has excellent flatness. Thus, in a casewhere an organic resin is applied as a material of the flattening film6, a level difference (elevation difference) caused by a structure (suchas the TFT 105) which is located below the flattening film 6 is hardlyreflected in an upper surface of the flattening film 6. This allows thecommon electrode 91 as well as the pixel electrode 71 to be formed on aflat surface.

As the flattening film 6, an organic resin film mainly composed ofacryl, or a spin-on-glass (SOG) film may be used, for example A relativedielectric constant of such a film as cited above is approximately 3 to4, and is lower than a relative dielectric constant (6 to 7) of SiN.Accordingly, in a case where an acrylic resin or an SOG film is appliedas the flattening film 6, a parasitic capacitance between the signalline 103 and a lower electrode (pixel electrode 71) is reduced. Thislessens an influence of a noise provided from the signal line 103, uponthe pixel electrode 71. Therefore, degradation in display quality due toa noise can be suppressed. Moreover, taking into account only lesseningof an influence of a noise, it is conceivable to apply an SiO filmhaving a dielectric constant which is comparable to a dielectricconstant of an SOG film, as the flattening film 6. However, an SiO filmis, like an SiN film, somewhat difficult to be flattened.

An organic resin film formed of a photosensitive material may be used asa material of the flattening film 6, for example. In such a case, anopening having a desired pattern can be formed in the flattening film 6by photolithography. Accordingly, the contact hole 61 can be easilyformed without etching. Then, by performing dry etching using theflattening film 6 having the contact hole 61 as an etching mask, it ispossible to form the contact hole 51 in the protective insulating film5.

The pixel electrodes 71 are provided on the flattening film 6 of theinsulating film 20. The pixel electrodes 71 are in a pattern in whichthe pixel electrodes 71 are placed in the pixels PX1, respectively. Thepixel electrodes 71 are formed of a transparent conductive material. Asa transparent conductive material, an indium zinc oxide (IZO), an indiumtin oxide (ITO), or the like is used, for example. The pixel electrode71 includes a connection conductive layer 71 a in addition to a plateelectrode part. The connection conductive layer 71 a is electricallyconnected to the drain electrode 42 by the drain contact hole 121. As aresult of inclusion of the connection conductive layer 71 a, the pixelelectrode 71 is electrically connected to the drain electrode 42. Thoughthe plate electrode part and the connection conductive layer 71 a of thepixel electrode 71 appear to be separated from each other in FIG. 5, theplate electrode part and the connection conductive layer 71 a of thepixel electrode 71 are joined to each other as shown in FIG. 4.

The interlayer insulating film 8 is provided on the pixel electrodes 71.The pixel electrodes 71 are covered with the interlayer insulating film8.

The common electrode 91 is provided on the interlayer insulating film 8.The common electrode 91 is formed of a transparent conductive material.As a transparent conductive material, IZO, ITO, or the like is used, forexample. The common electrode 91 and the pixel electrode 71 arepartially superimposed upon each other in plan view. In each of thepixels PX1, the common electrode 91 includes a slit 91 a (opening). Theslit 91 a faces the pixel electrode 71 via the interlayer insulatingfilm 8 in a thickness direction. Upon application of a voltage betweenthe pixel electrode 71 serving as a lower electrode and the commonelectrode 91 serving as an upper electrode, a fringe electric field isgenerated between the two electrodes. A fringe electric field comes outfrom the pixel electrode 71, develops upwardly via an opening of theslit 91 a of the common electrode 91, further develops horizontally (ina transverse direction) within the liquid crystal layer 400 (FIG. 1)provided above the common electrode 91, and then still further developstoward the common electrode 91 located on a lower side. As such, afringe electric field includes an electric field which is substantiallyhorizontal to the transparent insulating substrate 100. This horizontalelectric field drives a liquid crystal molecule in the liquid crystallayer 400 horizontally. As a result of this, a direction of polarizationof light passing through the above-stated liquid crystal molecule isappropriately changed for each pixel. Thus, desired displaying in whichthe pixel PX1 is dealt with as one unit can be achieved in the displayarea 101 (FIG. 2).

Moreover, an area where the common electrode 91 (FIG. 3) and the pixelelectrode 71 (FIG. 4) are superimposed upon each other is an area usedfor displaying in which the pixel PX1 is dealt with as one unit, namely,a display-pixel area 151 (FIG. 3). A light-shield film (black matrix)included in the color filter substrate 300 (FIG. 1) includes an openingin an area corresponding to the display-pixel area 151 in plan view.Also, the common electrode 91 lies over the plurality of pixels PX1, andso, the common electrode 91 also functions as the common line 106 (FIG.2).

The gate electrode 11, the gate insulating film 2, the channel layer 31,the source electrode 41, and the drain electrode 42 form the TFT 105 onthe transparent insulating substrate 100, below the pixel electrode 71and the common electrode 91. Tuning-on/off of the TFT 105 is controlledby a voltage supplied to the gate electrode 11 from the scanning line104. Also, a voltage is supplied to the source electrode 41 from thesignal line 103, based on signal data which is externally input. Withthe foregoing configuration, a voltage which is supplied from the signalline 103 and is based on signal data can be applied selectively to thedrain electrode 42 of a specific pixel PX1. A current (signal data) istransmitted to the pixel electrode 71 connected to the drain electrode42. Signal data is controlled by the IC chip 109 and the printed board110 which are connected to the terminal electrode 108 (FIG. 2). Thiscontrol is performed based on display data which is externally input. Inthe above-described manner, displaying in each of the plurality ofpixels PX1 is controlled based on display data which is externallyinput.

The metal layer 15, in conjunction with a part of the common electrode91, forms a laminated structure. In an example shown in FIG. 5, themetal layer 15 is provided on the interlayer insulating film 8. Themetal layer 15 is formed of a metal material. Terms, “a metal material”in this specification includes an alloy material. A metal material hasgenerally an excellent light-shield property.

The metal layer 15 includes a light-shield part 15 f. The light-shieldpart 15 f and the channel layer 31 overlap each other at least partiallyin plan view, or preferably, the light-shield part 15 f includes thechannel layer 31 in plan view, as shown in FIG. 4. The light-shield part15 f can block light which is incident from above the channel layer 31.Accordingly, electrical characteristics of the TFT 105 formed of anoxide semiconductor layer can be prevented from varying. As light whichis provided from above and travels toward the channel layer 31,irradiation light used in manufacture, diffracted light during operationof the liquid crystal display 500, or the like, can be cited. As lightused in manufacture, ultraviolet (UV) light with which the TFT substrate200 is irradiated during a cleaning process thereof, can be cited, forexample.

In a case where an organic resin film, in particular, an organic resinfilm formed of a photosensitive organic resin, is used as the flatteningfilm 6, the flattening film 6 tends to absorb a shorter wavelength ofvisible light and UV light. Such the flattening film 6 as stated abovesuppresses light incidence upon the channel layer 31 to a certaindegree. However, in order to achieve more satisfactory suppression, thelight-shield part 15 f is required. In a case where an SOG film is usedas the flattening film 6, unlike the case where an organic resin film isused, a shorter wavelength of visible light and UV light can easily passthrough the flattening film 6. For this reason, without the light-shieldpart 15 f, electrical characteristics of the TFT 105 using an oxidesemiconductor layer would be likely to vary greatly. Thus, inclusion ofthe light-shield part 15 f produces a significant effect.

The metal layer 15 is in contact with the common electrode 91. As aresult of this, the metal layer 15, as well as the common electrode 91,forms the common line 106 (FIG. 1). Accordingly, electrical resistanceof the common line 106 can be reduced. In a case where the metal layer15 extends along the scanning line 104, electrical resistance of thecommon line 106 can be remarkably reduced. This can reduce a potentialdifference which arises between different positions in the common line106 due to voltage drop. Thus, a voltage between the common electrode 91and the pixel electrode 71 can be prevented from varying due to theabove-stated potential difference. This suppresses variation amongdifferent ones of the pixels PX1 in fringe electric field generated inaccordance with a voltage between the common electrode 91 and the pixelelectrode 71. Therefore, unevenness in displaying in the liquid crystaldisplay 500 can be reduced. Also, by reducing electrical resistance ofthe common line 106, it is possible to reduce also unevenness caused dueto signal delay. As a material of the metal layer 15, a material havinglow resistivity is desirable, and a metal material such as Al, Ni, Mo,Nb, Ag, Nd, or Cu, or a metal alloy containing some of the above-statedmetal materials, is used, for example.

The metal layer 15 and the scanning line 104 overlap each other at leastpartially in plan view. Accordingly, it is possible to ensure a largearea for the metal layer 15 while keeping a proportion of thedisplay-pixel area 151 (FIG. 3) in the display area 101 (FIG. 1),namely, an aperture ratio, high.

Considering only the above-described functions of the metal layer 15,the metal layer 15 may be placed on either an upper surface or a lowersurface of the common electrode 91. However, when the metal layer 15 isprovided on an upper surface of the common electrode 91, the metal layer15 is located closer to the liquid crystal layer 400 (FIG. 1). Thisincreases a possibility that the liquid crystal layer 400 and the metallayer 15 may come into contact with each other. If a metal of differentkind is brought into contact with the liquid crystal layer 400, adirect-current voltage is applied to the liquid crystal layer 400 due toa contact potential difference. As a consequence, an adverse influencesuch as a change in composition of a liquid crystal material is given tothe liquid crystal layer 400 in some cases. In order to preventoccurrence of such a phenomenon as described above, it is preferablethat the metal layer 15 be placed on not an upper surface, but a lowersurface, of the common electrode 91. In other words, it is preferablethat the metal layer 15 be placed between the interlayer insulating film8 and the common electrode 91.

(Summary of Effects)

According to the first preferred embodiment, as shown in FIG. 5, thecommon electrode 91 is placed above the pixel electrode 71. As a resultof this, the common electrode 91 need not be placed between the TFT 105and the pixel electrode 71 formed of a transparent conductive materialin a thickness direction. This can allow an electrical path between theTFT 105 and the pixel electrode 71 to be made shorter than that in acase where the common electrode 91 is placed between the TFT 105 and thepixel electrode 71. This can reduce an area of a contact hole formingthe foregoing electrical path, while preventing electrical resistance ofthe electrical path from excessively increasing. Accordingly, an area ofa non-display-pixel area can be reduced. Thus, a high aperture ratio canbe easily ensured. Further, firstly, the metal layer 15 including thelight-shield part 15 f which blocks light travelling toward the channellayer 31 is provided. This suppresses deterioration of the channel layer31 formed of an oxide semiconductor, which is caused due to light. Thus,defective control of displaying which is caused due to deterioration ofthe channel layer 31 is suppressed. Secondly, the metal layer 15, inconjunction with a part of the common electrode 91, forms a laminatedstructure. This laminated structure forms an electrical path having lowresistance. As a result of this, a potential difference in the commonelectrode 91 within the TFT substrate 200 is reduced. Thus, unevennessin displaying of a display using the TFT substrate 200 is suppressed.Based on the above-described matters, it is possible to suppressoccurrence of defective displaying while ensuring a high aperture ratio.

Preferably, the metal layer 15 extends in a transverse direction in FIG.4, that is, along the scanning line 104. This can significantly reduceelectrical resistance of a current path which is associated with thecommon electrode 91 and extends along the scanning line 104, in otherwords, extends in a row direction of the TFT substrate 200 (FIG. 2).Thus, unevenness in displaying among the plurality of pixels PX1 in arow direction is suppressed.

Preferably, as shown in FIG. 4, the channel layer 31 is included in thegate electrode 11 in plan view. As a result of this, light travellingtoward the channel layer 31 from the transparent insulating substrate100 can be satisfactorily blocked by the gate electrode 11. Thus,deterioration of an oxide semiconductor which is caused due to light issuppressed. This further suppresses defective control of displayingwhich is caused due to deterioration of the channel layer 31 formed ofan oxide semiconductor.

Preferably, as shown in FIG. 5, the metal layer 15 is placed between theinterlayer insulating film 8 and the common electrode 91. As a result ofthis, the metal layer 15 is kept farther away from the liquid crystallayer 400 (FIG. 1). Thus, an adverse influence of a contact potentialdifference between the metal layer 15 and the liquid crystal layer 400upon the liquid crystal layer 400 can be prevented.

The insulating film 20 can include an organic resin film. As a result ofthis, flatness of a surface of the insulating film 20 can be easilyenhanced. Also, since the pixel electrode 71 and the signal line 103 areinsulated from each other by an organic resin film having a relativelylow dielectric constant, a parasitic capacitance between the pixelelectrode 71 and the signal line 103 is reduced. This can suppressdegradation in display quality, which is caused due to a noise providedto the pixel electrode 71 through the signal line 103.

The insulating film 20 can include an SOG film. As a result of this,flatness of a surface of the insulating film 20 can be easily enhanced.Also, since the pixel electrode 71 and the signal line 103 are insulatedfrom each other by an organic resin film having a relatively lowdielectric constant, a parasitic capacitance between the pixel electrode71 and the signal line 103 is reduced. This can suppress degradation indisplay quality, which is caused due to a noise provided to the pixelelectrode 71 through the signal line 103.

Second Preferred Embodiment

Referring to FIGS. 6 and 7, according to a second preferred embodiment,the TFT substrate 200 (FIGS. 1 and 2) includes a pixel PX2 in place ofthe pixel PX1 (FIGS. 4 and 5) described in the first preferredembodiment.

In the pixel PX2, the TFT substrate 200 includes a common transparentconductive layer 106 a. The common transparent conductive layer 106 a isplaced on the insulating film 20. In other words, the common transparentconductive layer 106 a is placed in the same layer as the pixelelectrode 71. The common transparent conductive layer 106 a is providedaway from the pixel electrode 71. The common transparent conductivelayer 106 a is formed of a transparent conductive material. Preferably,the common transparent conductive layer 106 a is formed of the samematerial that forms the pixel electrode 71. In such a case, the commontransparent conductive layer 106 a and the pixel electrode 71 can beformed simultaneously. This allows the common transparent conductivelayer 106 a to be formed without increasing the number of processes.

In the interlayer insulating film 8, acommon-transparent-conductive-layer contact hole 81 which reaches thecommon transparent conductive layer 106 a is provided. The metal layer15 includes a connection metal layer 15 a. The connection metal layer 15a is electrically connected to the common transparent conductive layer106 a by the common-transparent-conductive-layer contact hole 81. Thus,according to the second preferred embodiment, the common line 106 isformed of not only the common electrode 91 and the metal layer 15, butalso the common transparent conductive layer 106 a. As a result of this,electrical resistance of the common line 106 can be reduced. Thisfurther reduces a potential difference in the common electrode 91 withinthe TFT substrate 200. Thus, unevenness in displaying of a display usingthe TFT substrate 200 is further reduced.

It is preferable that the common transparent conductive layer 106 a andthe scanning line 104 overlap each other at least partially in planview. As a result of this, it is possible to ensure a large area for thecommon transparent conductive layer 106 a while keeping a proportion ofthe display-pixel area 151 (FIG. 3) in the display area 101 (FIG. 1),namely, an aperture ratio, high.

In a case where the common transparent conductive layer 106 a and thechannel layer 31 overlap each other at least partially in plan view, thechannel layer 31 is interposed between the common transparent conductivelayer 106 a and the gate electrode 11 in a thickness direction. In thiscase, when a potential difference arises between the common transparentconductive layer 106 a and the gate electrode 11, an electric field in athickness direction (in a vertical direction in FIG. 7) is applied tothe channel layer 31. If the applied electric field is large, thechannel layer 31 may possibly be deteriorated. A large electric field islikely to be applied to the channel layer 31 particularly at a time whenthe common-transparent-conductive-layer contact hole 81 is formed in theinterlayer insulating film 8 on the common transparent conductive layer106 a by dry etching. Thus, the channel layer 31 is likely to bedeteriorated particularly at a time of dry etching. In order to avoidsuch deterioration of the channel layer 31 as described above, it ispreferable that the common transparent conductive layer 106 a be placedoutside the channel layer 31 in plan view.

It is additionally noted that, in the other respects than describedabove, the configuration is substantially identical to theabove-described configuration according to the first preferredembodiment. Thus, components which are identical or similar to eachother are denoted by the same reference symbols, and description thereofis not repeated.

Third Preferred Embodiment

(Configuration)

Referring to FIGS. 8 and 9, according to a third preferred embodiment,the TFT substrate 200 (FIGS. 1 and 2) includes a pixel PX3, in place ofthe pixel PX1 (FIGS. 4 and 5) described in the first preferredembodiment.

In the pixel PX3, a lower gate contact hole 53 (first gate contact hole)which reaches the scanning line 104 is provided in the gate insulatingfilm 2. In the insulating film 20, an upper gate contact hole 122(second gate contact hole) which is joined to the lower gate contacthole 53 is provided. The upper gate contact hole 122 is formed of thecontact hole 52 and the contact hole 62 which are provided in theprotective insulating film 5 and the flattening film 6, respectively.

According to the third preferred embodiment, the metal layer 15 isprovided on a part of the flattening film 6 of the insulating film 20,as shown in FIG. 9. In other words, the metal layer 15 is placed in thesame layer as the pixel electrode 71. The pixel electrode 71 and themetal layer 15 are covered with the interlayer insulating film 8.Moreover, the light-shield part 15 f included in the metal layer 15 isplaced in the same manner as that in the first preferred embodiment, inplan view.

The metal layer 15 includes the connection metal layer 15 a. Theconnection metal layer 15 a passes through the lower gate contact hole53 and the upper gate contact hole 122, and reaches the scanning line104. In other words, the metal layer 15 is electrically connected to thescanning line 104 by the lower gate contact hole 53 and the upper gatecontact hole 122.

It is noted that, in the other respects than described above, theconfiguration is substantially identical to the above-describedconfiguration according to the first preferred embodiment. Thus,components which are identical or similar to each other are denoted bythe same reference symbols, and description thereof is not repeated.

(Effects)

According to the third preferred embodiment, like the first preferredembodiment, the common electrode 91 need not be placed between the TFT105 and the pixel electrode 71 formed of a transparent conductivematerial in a thickness direction. As a result of this, an electricalpath between the TFT 105 and the pixel electrode 71 can be made shorterthan that in a case where the common electrode 91 is placed between theTFT 105 and the pixel electrode 71. This can reduce an area of a contacthole which forms the foregoing electrical path, while preventingelectrical resistance of the electrical path from excessivelyincreasing. Accordingly, an area of a non-display-pixel area can bereduced. Thus, a high aperture ratio can be easily ensured. Further, themetal layer 15 including the light-shield part 15 f which blocks lighttravelling toward the channel layer 31 is provided. This suppressesdeterioration of the channel layer 31 formed of an oxide semiconductor,which is caused due to light. Thus, defective control of displayingwhich is caused due to deterioration of the channel layer 31 issuppressed. Based on the above-described matters, it is possible tosuppress occurrence of defective displaying, while ensuring a highaperture ratio.

Further, according to the third preferred embodiment, the metal layer 15is electrically connected to the scanning line 104. That is, the metallayer 15 and the scanning line 104 are electrically short-circuited toeach other. As a result of this, generation of a high electric fieldbetween the light-shield part 15 f included in the metal layer 15 andthe gate electrode 11 included in the scanning line 104 can be avoided.Accordingly, the channel layer 31 placed between the light-shield part15 f and the gate electrode 11 is prevented from being deteriorated dueto a high electric field. This further suppresses defective control ofdisplaying which is caused due to deterioration of the channel layer 31.Supposing that the metal layer 15 is not electrically connected to thegate electrode 11, a potential difference can possibly arise between themetal layer 15 and the gate electrode 11 for some reasons duringmanufacture or usage of the TFT substrate 200. In such a case, anelectric field in a thickness direction (in a vertical direction in FIG.9) is applied to the channel layer 31 placed between the light-shieldpart 15 f of the metal layer 15 and the gate electrode 11. If theapplied electric field is large, the channel layer 31 can possibly bedeteriorated.

Preferably, the metal layer 15 extends along the scanning line 104. Thiscan reduce electrical resistance of a current path which is associatedwith the scanning line 104 and extends along the scanning line 104, inother words, extends in a row direction. Accordingly, a potentialdifference among the scanning lines 104 in the TFT substrate 200 and asignal delay of the scanning line 104 are reduced. Thus, unevenness indisplaying among the plurality of pixels PX3 in a row direction isreduced.

(Modifications)

According to the above-described third preferred embodiment, as shown inFIGS. 8 and 9, the pixel electrode 71 and the metal layer 15 are placedso as not to overlap each other.

In a first modification, the metal layer 15 can include a connectionmetal layer stacked on the connection conductive layer 71 a, in additionto the connection metal layer 15 a. This reduces contact resistance withrespect to the drain electrode 42. Accordingly, a displaying propertycan be further improved. Moreover, in order to prevent the scanning line104 and the pixel electrode 71 from being short-circuited to each other,the additional connection metal layer should be separated from theconnection metal layer 15 a.

In a second modification, a connection conductive layer which is formedof the same transparent conductive material that forms the pixelelectrode 71, and is stacked on the connection metal layer 15 a, may beprovided. This reduces contact resistance with respect to the scanningline 104. Accordingly, a displaying property can be further improved.Moreover, in order to prevent the scanning line 104 and the pixelelectrode 71 from being short-circuited to each other, the additionalconnection conductive layer should be separated from the pixel electrode71. The second modification may be combined with the above-describedfirst modification.

Fourth Preferred Embodiment

According to a fourth preferred embodiment, the alignment layer 161(FIG. 1) is formed of a material having a photo-alignment property. Insuch a case, a method of manufacturing the liquid crystal display 500includes a process of forming the alignment layer 161 formed of amaterial having a photo-alignment property on the TFT substrate 200, anda process of carrying out photo-alignment treatment on the alignmentlayer 161. To carry out photo-alignment treatment changes an alignmentstate of a surface of the alignment layer 161 to a desired state.Photo-alignment treatment is carried out in such a manner that, afterthe alignment layer 161 is formed on an upper surface of the TFTsubstrate 200, the alignment layer 161 is irradiated with UV light fromabove or obliquely from above, for example. It is noted that, in theother respects than described above, the configuration is substantiallyidentical to the above-described configurations according to the firstto third preferred embodiments.

According to the fourth preferred embodiment, in photo-alignmenttreatment, light travelling toward the channel layer 31 is blocked bythe light-shield part 15 f. This suppresses deterioration of the channellayer 31 formed of an oxide semiconductor, which is caused due to light,as compared to a case where the light-shield part 15 f is not provided.Accordingly, defective control of displaying which is caused due todeterioration of the channel layer 31 is suppressed.

Fifth Preferred Embodiment

(Configuration)

Referring to FIG. 10, the external line 107 (FIG. 2) typically includesan external gate line 107 a (first line) and an external source line 107b (second line). The external gate line 107 a is placed on thetransparent insulating substrate 100. In other words, the external gateline 107 a is placed in the same layer as the scanning line 104. Theexternal gate line 107 a is formed of the same material that forms thescanning line 104. Accordingly, the external gate line 107 a can beformed simultaneously with the scanning line 104. The external sourceline 107 b is placed on the gate insulating film 2. In other words, theexternal source line 107 b is placed in the same layer as the signalline 103. The external source line 107 b is formed of the same materialthat forms the signal line 103. Accordingly, the external source line107 b can be formed simultaneously with the signal line 103. Because ofthe configuration of the external line 107, the external gate line 107 aand the external source line 107 b are electrically connected to eachother in the frame area 102 (FIG. 2) in some cases. The fifth preferredembodiment will discuss such cases.

According to the fifth preferred embodiment, in the frame area 102, acontact hole 55 is provided in the gate insulating film 2, and a contacthole 54 and a contact hole 56 are provided in the protective insulatingfilm 5. Also, a contact hole 64 and a contact hole 66 are provided inthe flattening film 6. The contact hole 64, the contact hole 54, and thecontact hole 55 are joined to each other, to thereby form an externalgate contact hole 124 (first contact hole) passing through theinsulating film 20 and the gate insulating film 2. The contact hole 66and the contact hole 56 are joined to each other, to thereby form anexternal source contact hole 126 (second contact hole) passing throughthe insulating film 20.

The metal layer 15 includes a connection metal layer 15 p placed withinthe frame area 102. The connection metal layer 15 p is electricallyconnected to the external gate line 107 a by the external gate contacthole 124, and is electrically connected to the external source line 107b by the external source contact hole 126. As a result of this, theexternal gate line 107 a and the external source line 107 b areelectrically connected to each other. According to the fifth preferredembodiment, like the first or second preferred embodiment, the metallayer 15 is placed on the interlayer insulating film 8. To this end, acontact hole 82 and a contact hole 83 which are joined to the externalgate contact hole 124 and the external source contact hole 126,respectively, are provided in the interlayer insulating film 8.

A connection conductive layer 71 p may be provided in the frame area102. The connection conductive layer 71 p is placed on the insulatingfilm 20. In other words, the connection conductive layer 71 p is placedin the same layer as the pixel electrode 71 (FIG. 5 or FIG. 7). Also,the connection conductive layer 71 p can be formed of the sametransparent conductive material that forms the pixel electrode 71.Accordingly, the connection conductive layer 71 p can be formedsimultaneously with the pixel electrode 71. By stacking the connectionconductive layer 71 p on the connection metal layer 15 p in the externalgate contact hole 124, it is possible to reduce contact resistance. Bystacking the connection conductive layer 71 p on the connection metallayer 15 p in the external source contact hole 126, it is possible toreduce contact resistance. Respective parts of the connection conductivelayer 71 p, which are placed in the external gate contact hole 124 andthe external source contact hole 126, are not necessarily required to bejoined to each other. However, in a case where the parts are joined toeach other as shown in the figure, electrical resistance between theexternal gate line 107 a and the external source line 107 b can befurther reduced.

A connection conductive layer 91 p may be provided in the frame area102. The connection conductive layer 91 p is placed on the interlayerinsulating film 8. In FIG. 10, the connection conductive layer 91 p isplaced on a part of the interlayer insulating film 8, where theconnection metal layer 15 p is provided. In other words, the connectionconductive layer 91 p is placed in the same layer as the commonelectrode 91 (FIG. 5 or FIG. 7). Also, the connection conductive layer91 p can be formed of the same transparent conductive material thatforms the common electrode 91. Accordingly, the connection conductivelayer 91 p can be formed simultaneously with the common electrode 91. Bystacking the connection conductive layer 91 p on the connection metallayer 15 p in the external gate contact hole 124 and the contact hole82, it is possible to reduce contact resistance. By stacking theconnection conductive layer 91 p on the connection metal layer 15 p inthe external source contact hole 126 and the contact hole 83, it ispossible to reduce contact resistance. Respective parts of theconnection conductive layer 91 p, which are placed in the external gatecontact hole 124 and the external source contact hole 126, are notnecessarily required to be joined to each other. However, in a casewhere the parts are joined to each other as shown in the drawings,electrical resistance between the external gate line 107 a and theexternal source line 107 b can be further reduced.

It is noted that, in the other respects than described above, theconfiguration is substantially identical to the above-describedconfiguration according to the first or second preferred embodiment.Thus, components which are identical or similar to each other aredenoted by the same reference symbols, and description thereof is notrepeated.

(Effects)

According to the fifth preferred embodiment, the external gate line 107a and the external source line 107 b are connected to each other by theconnection metal layer 15 p. The connection metal layer 15 p is formedof a metal which is a material having generally lower resistivity thanresistivity of a transparent conductive material. This allows theexternal gate line 107 a and the external source line 107 b to beconnected to each other with low resistance. Accordingly, lineresistance and signal delay of the external line 107 including theexternal gate line 107 a and the external source line 107 b can bereduced. In other words, line resistance and signal delay of theexternal line 107 which extends to the display area 101 can be reduced.Thus, a displaying property can be improved.

Moreover, the connection metal layer 15 p placed in the frame area 102(FIG. 2) can be formed simultaneously with the other part of the metallayer 15. Accordingly, an increase in the number of processes, which mayotherwise occur due to inclusion of the connection metal layer 15 p, canbe avoided.

(First modification)

At least parts of a component which function similarly to the externalline 107 (FIG. 2) may be placed dispersedly within the display area 101.This is applied to a case where driving circuits are dispersedly placedwithin the display area 101, for example. In this case, theabove-described connection metal layer 15 p can be placed in not theframe area 102 but the display area 101, or can be placed in both of theframe area 102 and the display area 101.

(Second Modification)

The above-described fifth preferred embodiment has discussed a casewhere the connection metal layer 15 p (FIG. 10) is applied to theconfiguration according to the first or second preferred embodiment(FIG. 5 or 7). Meanwhile, the connection metal layer 15 p (FIG. 11)according to the present modification can be applied to theconfiguration according to the third preferred embodiment (FIG. 9). Inthis case, the connection metal layer 15 p (FIG. 11) of the metal layer15, together with the connection metal layer 15 a and the light-shieldpart 15 f (FIG. 9), is placed on the flattening film 6 of the insulatingfilm 20. Accordingly, so far as placement of the connection metal layer15 p is concerned, the contact hole 82 and the contact hole 83 in theinterlayer insulating film 8 are not necessarily required. However,those contact holes should be required in a case where the connectionconductive layer 91 p is provided.

(Third Modification)

An electronic circuit having function of the IC chip 109 (FIG. 2) can beformed in the frame area 102 with the use of processes similar tomanufacturing processes of the TFT 105. The external gate line 107 a andthe external source line 107 b can be used as lines in the foregoingelectronic circuit. This reduces line resistance and signal delay in theforegoing electronic circuit. Accordingly, a displaying property can beimproved.

While each of the above-described preferred embodiments has discussed indetail a case where an FFS mode which is of a general type as a mode ofdriving liquid crystal is used, any mode other than an FFS mode which isof a general type may be used. Also, while each of the above-describedpreferred embodiments has discussed in detail a case where a liquidcrystal display is used as a display to which a TFT substrate isapplied, a TFT substrate may be applied to any display other than aliquid crystal display.

The present invention allows any arbitrary combination of the preferredembodiments, and appropriate modification and omission of each of thepreferred embodiments, within the scope of the invention.

What is claimed is:
 1. A thin-film transistor substrate which includes adisplay area having a plurality of pixels which are arranged in amatrix, comprising: a supporting substrate; a gate line which isprovided on said supporting substrate and includes a gate electrodeplaced in each of said pixels; a gate insulating film with which saidgate line is covered; a channel layer which is provided on each of saidgate electrodes via said gate insulating film and is formed of an oxidesemiconductor; a source line which is placed in each of said pixels andincludes a source electrode which is in contact with said channel layer;a drain electrode which is placed in each of said pixels, and is incontact with said channel layer, said drain electrode being distant fromsaid source electrode; a first insulating film which is provided on saidchannel layer, said source line, and said drain electrode, and includesa drain contact hole which reaches said drain electrode; a pixelelectrode which is provided on said first insulating film in each ofsaid pixels, and includes a connection conductive layer electricallyconnected to said drain electrode by said drain contact hole, said pixelelectrode being formed of a transparent conductive material; a secondinsulating film with which said pixel electrode is covered; a commonelectrode which is provided on said second insulating film, and includesan opening facing said pixel electrode in a thickness direction, saidcommon electrode being formed of a transparent conductive material; anda metal layer which forms a laminated structure in conjunction with apart of said common electrode, and includes a light-shield part whichoverlaps said channel layer at least partially in plan view.
 2. Thethin-film transistor substrate according to claim 1, further comprising:a common transparent conductive layer which is provided away from saidpixel electrode on said first insulating film, and is formed of atransparent conductive material, wherein acommon-transparent-conductive-layer contact hole which reaches saidcommon transparent conductive layer is provided in said secondinsulating film, said metal layer is electrically connected to saidcommon transparent conductive layer by saidcommon-transparent-conductive-layer contact hole, and said commontransparent conductive layer is placed outside said channel layer inplan view.
 3. The thin-film transistor substrate according to claim 1,wherein said metal layer extends along said gate line.
 4. The thin-filmtransistor substrate according to claim 1, wherein said metal layer isplaced between said second insulating film and said common electrode. 5.The thin-film transistor substrate according to claim 1, wherein saidchannel layer is included in said gate electrode in plan view.
 6. Thethin-film transistor substrate according to claim 1, wherein said firstinsulating film includes an organic resin film.
 7. The thin-filmtransistor substrate according to claim 1, wherein said secondinsulating film includes a spin-on-glass film.
 8. The thin-filmtransistor substrate according to claim 1, further comprising: a firstline which is provided on said supporting substrate and is formed of thesame material that forms said gate line; and a second line which isprovided on said gate insulating film and is formed of the same materialthat forms said source line, wherein said metal layer includes aconnection metal layer, and said connection metal layer is electricallyconnected to said first line by a first contact hole which passesthrough said first insulating film and said gate insulating film, and iselectrically connected to said second line by a second contact holewhich passes through said first insulating film, so that said first lineand said second line are electrically connected to each other.
 9. Thethin-film transistor substrate according to claim 8, wherein saidthin-film transistor substrate includes a frame area provided outsidesaid display area, and said connection metal layer is placed within saidframe area.
 10. A liquid crystal display comprising: the thin-filmtransistor substrate according to claim 1; a counter substrate placed ata distance from said thin-film transistor substrate; and a liquidcrystal layer held between said thin-film transistor substrate and saidcounter substrate.
 11. The liquid crystal display according to claim 10,further comprising an alignment layer which is provided on saidthin-film transistor substrate and causes alignment of said liquidcrystal layer, wherein said alignment layer is formed of a materialhaving a photo-alignment property.
 12. A thin-film transistor substratewhich includes a display area having a plurality of pixels which arearranged in a matrix, comprising: a supporting substrate; a gate linewhich is provided on said supporting substrate and includes a gateelectrode placed in each of said pixels; a gate insulating film withwhich said gate line is covered, said gate insulating film including afirst gate contact hole which reaches said gate line; a channel layerwhich is provided on each of said gate electrodes via said gateinsulating film and is formed of an oxide semiconductor; a source linewhich is placed in each of said pixels and includes a source electrodewhich is in contact with said channel layer; a drain electrode which isplaced in each of said pixels, and is in contact with said channellayer, said drain electrode being distant from said source electrode; afirst insulating film which is provided on said channel layer, saidsource line, and said drain electrode, said first insulating filmincluding a second gate contact hole which is joined to said first gatecontact hole, and including a drain contact hole which reaches saiddrain electrode; a pixel electrode which is provided on said firstinsulating film in each of said pixels, and includes a connectionconductive layer electrically connected to said drain electrode by saiddrain contact hole, said pixel electrode being formed of a transparentconductive material; a metal layer which is provided on a part of saidfirst insulating film and includes a light-shield part which overlapssaid channel layer at least partially in plan view; a second insulatingfilm with which said pixel electrode and said metal layer are covered;and a common electrode which is provided on said second insulating film,and includes an opening facing said pixel electrode in a thicknessdirection, said common electrode being formed of a transparentconductive material, wherein said metal layer is electrically connectedto said gate line by said first gate contact hole and said second gatecontact hole.
 13. The thin-film transistor substrate according to claim12, wherein said metal layer extends along said gate line.
 14. Thethin-film transistor substrate according to claim 12, wherein saidchannel layer is included in said gate electrode in plan view.
 15. Thethin-film transistor substrate according to claim 12, wherein said firstinsulating film includes an organic resin film.
 16. The thin-filmtransistor substrate according to claim 12, wherein said secondinsulating film includes a spin-on-glass film.
 17. The thin-filmtransistor substrate according to claim 12, further comprising: a firstline which is provided on said supporting substrate and is formed of thesame material that forms said gate line; and a second line which isprovided on said gate insulating film and is formed of the same materialthat forms said source line, wherein said metal layer includes aconnection metal layer, and said connection metal layer is electricallyconnected to said first line by a first contact hole which passesthrough said first insulating film and said gate insulating film, and iselectrically connected to said second line by a second contact holewhich passes through said first insulating film, so that said first lineand said second line are electrically connected to each other.
 18. Thethin-film transistor substrate according to claim 17, wherein saidthin-film transistor substrate includes a frame area provided outsidesaid display area, and said connection metal layer is placed within saidframe area.
 19. A liquid crystal display comprising: the thin-filmtransistor substrate according to claim 12; a counter substrate placedat a distance from said thin-film transistor substrate; and a liquidcrystal layer held between said thin-film transistor substrate and saidcounter substrate.
 20. The liquid crystal display according to claim 19,further comprising an alignment layer which is provided on saidthin-film transistor substrate and causes alignment of said liquidcrystal layer, wherein said alignment layer is formed of a materialhaving a photo-alignment property.